Introduction
This page describes my design work to develop my own implementation of a 16 bit AT PC system in ATX form factor. The design goal is to create a PC system fully compatible with the industry standard 16 bit AT technology developed by IBM, however to also offer various improvements which will make using such a PC much more easy and in such more enjoyable in my opinion, from a perspective of comfortable and user friendly functionality. This design, which will ultimately be published on my GitHub pages, is intended to be used solely and exclusively for retro PC hobby purposes, for retro computing enthousiasts like myself. The design will implement a version of logic circuits which is most appealing to me based on my experience with creating mainboard systems while at the same time attempting to keep the system fully compatible with the industry standard 16 bit PC. I will also be making various changes to the design in order to modify the system somewhat. This is not done for simplification persé but rather to reduce total board space and increase system stability and expandability in a more modern fashion. I will make attempts to do the whole design without using programmable logic altogether, if conventional logic ICs can possibly prove to be sufficient in the timing constraints necessary for the new design to function properly.
After finishing my XT PC mainboard design project with revision 3, and publishing the designs on GitHub, I started studying the IBM 5170 AT PC circuits, to see if it would be possible to design a 16 bit AT compatible PC in such a way which could be attractive to me. The "secret sauce"-alike AT circuits created by IBM in the 5170 proved to be quite intrigueing indeed, the more I studied them. Especially the fact that the AT design is backwards-compatible with XT expansion cards and how IBM implemented this by using the 8 to 16 bit databus translation method. This principle is also supported in the 80286 CPU itself by Intel. IBM implemented this design in their 16 bit industry PC standard mainboards which started a very big number of clone designs from various PC manufacturers. The most interesting variations of AT PC designs to me are the early "discrete chipset" versions, meaning that there actually is no chipset used in the design and that it is fully done in TTL logic and a few PALs and PROM chips. This design method used in the IBM 5170 PC and derived designs by others are particularly interesting because these still can show the interfacing mechanisms in actual logic chips rather than a few integrated logic design parts in the form of one or more PC chipset ICs, which would not at all be interesting for someone like me who is trying to understand how the 16 bit industry PC actually functions.
Designing my own version of the IBM AT PC could serve to open up various future developments which I will research and explore later on to see what else could be possible to further develop a 16 bit PC system. I plan to include these features early on in the prototype designs. I will publish my AT designs on GitHub once I have developed a version which is stable enough and worthy to publish them.
The most important part of this project will of course be the mainboard PCB. In addition I will develop a SRAM memory module and CPU module to accompany this mainboard. This method provides several advantages:
- saving PCB space which can be used for including more features in the mainboard design
- offering the possibility to upgrade the CPU and memory, including the option to emulate a 16 bit CPU with modern technology which could possibly result in an even faster system, my dream is to create a mainboard which would be compatible with a 16 bit version of a 80486 or later CPU and thus being capable of running faster DOS games such as Doom and being able to run Windows 95 with reasonable speeds.
I will integrate various necessary PC interfaces and the realtime clock with non volatile CMOS configuration RAM on the mainboard. I will include as many of the typically necessary expansion interfaces onboard as space can permit on the mainboard PCB. For the final completion of a 16 bit PC system, I will implement 7 fully functional 16 bit ISA slots on each mainboard revision of this project.
Path of development
I will develop this project in a blog fashion, thus the whole design path and revisions of the project will follow chronologically in this single web page.
Phase 1: study of existing designs and finding physical reference hardware examples
I have bought several old example mainboards from the 1980s and found myself initially rather unlucky to come across several unreliable mainboards. The reasons for being unreliable were probably PCB tracks which had become compromised due to the age and previous handling of the mainboards, damage in transport, as well as discovering some poor manufacturing quality such as one particularly badly warped NCR branded PCB, soldered to the ISA slots in pretty warped condition. Straightening such a 4 layer PCB after being mishandled by terrible wave soldering techniques will probably not be an option, especially after the PCB has already proven unreliable.
Anyway, after doing some testing, troubleshooting and repair work on the last mainboards I was lucky enough to come across, I finally now have two reference hardware example mainboards which appear to now be functioning reliably:
IBM 5170 mainboard "type 3"
The 5170 PC mainboard by IBM which I have studied and repaired is showing particularly beautiful and excellent design and manufacturing quality which I am really delighted with. I found a new appreciation for IBM in those years with respect to design and manufacturing quality after being able to compare between different brands. Though the design I studied contained a small flaw corrected with a few wires, besides this it's really remarkably well made.
The 5170 mainboard was made in two revisions, type 1 which uses smaller capacity DRAMs and a larger form factor square shaped PCB, and type2/3 which implements the same PCB design using a smaller rectangular PCB size as well as larger DRAMs, though unfortunately still only containing 512KB of RAM onboard. Initially I got a lot of RAM parity errors in random areas and the occasional error 107 System Board Error, the so-called "HOT NMI TEST". After desoldering and replacing a few logic ICs which proved to function only marginally, these errors are fully gone from the system.
ARC X286 Model 12 mainboard
The final reference hardware example I bought which proved to be worthy and useful for my project is a X286 Model 12 mainboard by ARC. This mainboard is also of a very reasonable manufacturing quality, however I found it necessary to desolder a whole quadrant of the PCB due to corrosion damage by RTC clock battery chemicals. It was necessary to extensively remove degraded solder from the PCB and from the legs of ICs in the area, and resolder all the components and repair a few traces, replacing all the dangerous tantalum capacitors and some transistors in the battery circuits. After all the work I have done on it, the ARC looks reasonable enough and functions in a stable fashion.
Creating KiCad design schematics of the reference hardware example mainboards
After having two functional mainboards which can serve as reference hardware examples for testing and design evaluation purposes, I proceeded to first draft the whole IBM 5170 type 2 mainboard in a single sheet KiCad schematic. Doing this work, it also serves to get more familiar with the various system circuit areas and how they function as a whole. Having a single sheet schematic allows for easier location of circuit areas by doing searches and pans throughout the schematic. Additionally it offers the advantage of creating the full netlist which I will be verifying by beeping out all the net connections on the IBM mainboard.
After completing the IBM 5170 schematic, I am creating the schematic for the ARC based on that. First I renamed all the components to their ARC counterpart designations, and next I verified the gate connections. In doing this I discovered a design oversight in the ARC mainboard, an open input on a '08 AND logic gate in the directional control logic for a databus transceiver. This open input doesn't seem to impact the system, apparently the 74F08 regards an open input as a logic 1 in this case. I have tested several solutions where I prefer to connect the open input pin 13 with the adjacent VCC pin 14.
I may need to consider only using the IBM schematics as a source because the ARC seems to have some trouble with hardware detection using MR BIOS. Strangely enough, on rare occasions the ARC mainboard POST fails to detect the standard ports of the PC, IDE, FDD, LPT, COM. It then lists the "changes" and saves the CMOS settings which reflects these ports to be missing. After the next reboot, detection functions again and the MR BIOS prompts with the list of detected ports and saving the CMOS once more after a BIOS entry upon user keypress. After this second save, the PC boots normally again, and continues to operate normally. The hardware detection problem seemed to be an issue with my first ARC mainboard as well, which at the time I attributed to a defect caused by power loss, however after this second mainboard is also showing something similar, apparently there is a lingering problem somewhere. Though I can't exclude that the higher clock frequency of the ARC has something to do with it to be somehow attributing to these symptoms.
Mouse control
While testing varous 286 and 386 mainboards, I noticed that mouse control particularly in Windows was not ideal. I was using a serial ball mouse since these PCs don't feature a PS/2 mouse port. For this new project I have done some research to see what the alternatives could be for a serial mouse.
The best solution so far is the USB to serial mouse adapter project by GitHub user LimeProgramming.
Adam has created an excellent open source project using the RP2040 controller on a Raspberry Pi Pico PCB. The RP2040 controller, though arguably having even more processing power than a 286, is a cheap small device which conveniently offers USB port capability which was used in his GitHub project to interface with the USB mouse.
I have built a simplified prototype wired up version of the USB to serial mouse adapter and tested it with my 286 mainboard via a modified multi I/O card where I removed the +/- 12V level converters and plugged my prototype board directly onto the COM2 header and I can report that it works perfectly with my Logitech USB wireless mouse. The mouse pointer travel speed can be configured by two jumpers which is sufficient to achieve a really great result using 640x480 VGA resolution in Windows. This excellent solution by Adam is a definate keeper from now on!
I will integrate a simplified version of Adams project in my new 286 mainboard design, which will feature a USB connector in the I/O shield area for using a modern USB mouse. The RP2040 will be featured on a small plug in PCB which will sit vertically in relation to the mainboard on a small header to reduce the footprint size necessary on my mainboard PCB layout. I may try to use a stamp sized version of a RP2040 PCB on a plugin PCB which would be the smallest solution other than soldering the RP2040 components directly which are rather tiny compared to other components on the mainboard. The serial mouse data will be passed to a regular COM2 UART chip using TTL level serial connections with the RP2040, omitting the +/-12V RS232 logic. The code in the RP2040 flash will be the original code as featured in Adams project which suits my mainboard perfectly.
Going forward with the design
First I have removed all the DRAM, parity and refresh logic, after which the DMA handshaking logic required some modifications since refresh pulse generation was tightly integrated into these circuits by the IBM designers.
Removing parity on an actual IBM 5170 turned out to be really simple, just remove U85 and you're done. I have done some repairs on the parity circuits on my 5170 mainboard after which I made this discovery. Anyway I know the parity problem and fixed it. I am now testing the 5170 without U85 for a few weeks which works fine.
Next I have designed a completely new memory decoder and memory subsystem which consists of 1MB SRAM ICs for creating 16 bit conventional memory, 4MB additional SRAM for a block of extended memory, so total of 5MB of SRAM ICs are used.
The first megabyte of RAM sacrificed a certain amount of RAM space so I could keep a straightforward memory decoding scheme which I prefer rather than doing elaborate decoding. I have made an optional UMB space of 128KB of 16 bit RAM available with jumper selections for block D and E.
Next there is the BIOS memory space of 64KB at 0F0000 until 0FFFFF which supports the 16 bit AT system BIOS ROM function in two 8 bit EPROMs of 32kb each.
Additionally there is 32kb of 8 bit wide option ROM space in the form of an EPROM socket available at 0C8000 until 0D0000, where various option ROM code blocks can be added to the system using an EPROM or EEPROM. One useful example will be the 16 bit AT version of XT-IDE of course, though I may look at integrating it into the BIOS space if there is any vacant area there.
I have added my ATX power on and reset logic into the system with a proper 2 second power on reset delay and a 500 millisecond period of extra delay to allow ATX power voltages to stabilize first, preceeding to the 2 second RESET hold which then follows before releasing RESET for the BIOS POST to start.
The XMS memory has a 16 bit wide layout, ranging from 100000 until 4FFFFF which amounts to 4MB of XMS memory on top of the first megabyte of memory space. I assume this is sufficient for any programs capable to run on the 80286 CPU, at least for now.
I am now working on the PCB to maintain the slot locations and mounting hole coordinates which will save me some time not needing to redo those. The original IBM design provided 8 AT ISA slots, however I plan to provide 7 expansion slots more in ATX style since many interfaces will be included onboard, requiring not too many additional adapter cards to gain a full AT PC system.
The SRAM chips will be featured on a Memory Card design using a 54 pin connector. This will reduce the footprint space needed for the system memory and allow more room for the interfaces I plan to include onboard.
One of the steps I am working on is to replace the PAL and PROM logic. I have already replaced 20 pin PROM chip U72 which is no longer needed in the system. I found some PAL data at this Vintage Computer Federation page.
Users newold86 and eeguru did some quite useful work to extract output data and recreated the logic equations for the PAL16L8 ICs U87 and U130 in an efficient manner. I will do some work to draw out these equations in logic gates and do some deduction whether this could be assumed to indeed be correct. I have some plans to create a few circuit boards and test it out. I do want to switch to conventional equivalent logic so I first need to get a picture of the logic in the PALs so I can have a reference to then try to modify into some conventional TTL ICs, that is the plan for now. I will first check whether these PAL extractions can function which can save me some design time which I can spend on other stuff in the project.
I have made some modifications to the RTC circuits to possibly accommodate a DS12885 RTC chip, which is rather quirky and different from the MC146818 used by IBM and others. I just have a supply of the DS12885 so I will be using one. The DS12885 differs mainly because it has internal battery management and checking, and expects the power on pin 24 to drop when the PC is powered down. If this is all not satisfactory to the DS12885 internal checks, it will fail to function. I have already tested the modifications in place on an actual IBM 5170 mainboard where I made a VCC pin which I wired to a 1 pin connector from the DS12885.
I have two development phases moving forward now in december of 2023, the first phase is designing an ISA card with some additional connectors to route about 30 signals from the 5170. The ISA card contains the BIOS, all the SRAM and option ROM socket. I added a power on reset circuit as well since the IBM is lacking a circuit of its own for this specific purpose and relies on a PSU to do it, which I dislike. I will need to modify the 5170 extensively, removing all the DRAM ICs, memory buffers and various other stuff for testing. This is a precarious operation to maintain the function of circuits which will remain in use and are required for the system to operate with the SRAM modification.
The next development phase will be the first revision of the actual ATX mainboard design, which is also under development right now. I will first let JLCPCB make the ISA memory card and memory module PCB, and after doing some testing with it on the IBM 5170 I will proceed to complete the ATX mainboard revision 1 design and order this board from the PCB factory in China.
