Z80-PC Development

Mainboard

I have done various PCB design and building projects since the late 90's. Usually those projects were Z80 based. I started with the ZX80 and ZX97 Lite, and continued with the ZX81 Issue 4. With every new project I tried to raise the design level. I did some DIP projects and also some SMD ones after doing a lot of SMD soldering for my work.

I have always had the wish to build up a more complete system which has the capabilities similar to a classic PC. When I found some projects based on the RC2014 retrobrew Z80 system (invented by Spencer Owen), and especially after seeing the very excellent BIOS and bankswitching system project called ROMWBW, which was created and is being maintained by Wayne Warthen, I knew that I had found something special that would be a really feature rich system to build and try to expand further!

I decided to build up my own Z80 system, inspired by the ideas I have seen on various pages made by users(Karl Brokstad, Spencer Owen, Scott Baker, J.B. Langston, Marco Maccaferri) who were building RC2014 systems with their own hardware additions and modifications. I decided to design some basic circuits from KiCad schematics and logically combine some things. I spent some time testing a couple of hand wired PCBs and came to the conclusion that this system with the current expandibility would really deserve and benefit from a mainboard PCB design.

This mainboard serves to set a known functional hardware base from which I can develop both in hardware and software. The mainboard is intended as a through-hole only project, making it easier to solder. There is one exception, a 8 pin USB to UART chip, which is however purely optional and can be replaced by a small plug in PCB which plugs into the included header. Additionally, an ethernet controller is a 100pin SMD chip, which should be soldered to an adapter board, yet to be designed.

One thing which I concluded most notably after my prototype testing is that amongst the many designs supported by drivers in ROMWBW, one thing was especially missing, a fast graphics adapter which could connect to a PC monitor and display in higher resolutions. So this is definately on my wish list to develop one! I am doing the research for this plan now.

Long story short: I redesigned the IO decoder circuits, integrated some buffering, split the Z80 bus in three sections:

  • Memory bus (memory access only)
  • I/O bus (I/O devices only)
  • Expansion bus (an extension of the I/O bus which only becomes active if an "offboard" expansion device responds to the IO address it is designed on.

I tested with various circuits to power on and off an industry standard ATX power supply, and designed a reset circuit. These formed the basis of a mainboard design which has the following functions:

  • Z80 CPU
  • Z80 CPU expansion connector (replacing Z80 or take control of system with other CPU)
  • one flash ROM memory chip of 512kb according to ROMWBW bankswitching system
  • 6 SRAM memory chips of 512kb each, one of which can be jumpered to become an extra flash ROM if needed
  • GPU slot which contains access to shared RAM of 512 kb and two latched I/O handshake ports
  • 6 device expansion card edge slots (device I/O only)
  • PPIDE harddisk controller port
  • RCWDC floppy drive bus
  • ACIA serial port for connection to a IBM PC via standard A-B usb cable
  • TMS9918 CRT controller NTSC composite output
  • dual YM2149 mixed to 3,5mm line output connector (trimmer adjustable volume)
  • dual SN76489 sound chip, mixed to same 3,5mm line output connector (trimmer adjustable volume)
  • cassette tape output and input similar to Sinclair home computers
  • VT82C42 PS/2 keyboard and mouse ports
  • DS1302 realtime clock chip with offboard battery connection header
  • RTL8019AS ethernet interface (using a small SMD-to-pins plug in PCB)
  • ATX power supply control to standard 24 connection ATX power connector (including soft-off, made with conventional logic ICs)
  • power-on reset circuit with clock based timing (also with conventional logic chips)
  • 18 LED outputs for signalling various system functions, on 3 small headers, custom LED front panel is planned

Not everything on the list is supported by software drivers yet:

  • the cassette tape loader software needs to be written (great starter project!)
  • PS/2 mouse function is not made yet
  • Realtek ethernet connection software needs to be developed, though I have read that there is NE2000 code which might be compatible, and Realtek does offer many support files which may contain helpful information!
  • dual YM sound, I am not sure if there is some software which could do it.

Hardware design for the GPU controller PCB is pending, I am currently doing research to determine what solution would offer the best functionality. I am looking at "bare metal" programming the ARM processor on a Raspberry Pi zero board, and also I am considering an FPGA board with the ARM CPU included as a soft processor core.

The problem when looking into programming the Broadcom 2835 on the Raspberry Pi Zero is that this Broadcom chip is basically made to form the core of a mobile phone, and is much more complex than a mere ARM processor. In order to use it purely as a processor and redesignate it to completely new functions, I will need to determine the right way to do it, and how to make use of the GPIO pins in order to interface to the SRAM and handshaking latch circuits shared with the Z80, and how to output the VGA data to a screen. The big advantage of the Broadcom chip however is the very low cost price and amount of processing power and coupled memory space which can become available when using this chip.

There is a GPU slot present on the mainboard which passes the VGA signals through to the VGA connector already present in the IO Shield area.

The mainboard is ordered from a Chinese PCB manufactorer last weekend and already en route to my home, I am expecting it to clear customs in Germany at some time, after which I hope to have the first boards for testing!

I have implemented full buffering on the buses, and redesigned the IO decoders in a universal method. I still will need to test if with all these circuits the timing will be sufficient! I will update this page as soon as I have more news about this.

PCB image

Update: Prototype mainboard

13-2-2022

A photo of the assembled mainboard.
A photo of the assembled mainboard.

I have received the manufactured mainboard PCBs from JLCPCB (a big recommendation from me!) and built one up. At first I have connected all the ICs which were necessary for basic function and starting via ROMWBW HBIOS software.

During my test work I have found some issues, as I expected. I was not able to test several things on my previous hand wired setup because I would have to dramatically alter all the PCBs in such a way that it would have been much more work than manufacturing and building up this mainboard, and would have been considerably less stable and solid.

The issues I have found were:

  • I need to rename some signals in the ROMWBW bankswitching circuits because I used the naming convention "MAxx" for all the address lines which control the memory ICs after separating the memory and IO bus. Specifically the A14 and A15 lines need to be taken from the Z80 directly to the bankswitching register ICs, which then control the memory IC MA14 and MA15 lines amongst others. I have disconnected those pins on the registers with an extra socket inbetween, and taken the signals from the CPU directly to the registers with a few wires.
  • There is an I/O timing issue (of course!) with the decoder which creates the IO direction signal for the I/O data buffer. Apparently one extra gate in the signal path from /IORQ is creating a delay which is too long to get the data on the bus fast enough for the CPU to handle it. I have taken out the /IORQ and /M1 evaluation gate for the time being, since it is only necessary for certain /INTACK events which are currently not used. I will see how I can solve the problem to later include /M1 for the /INTACK conditions.
  • I wrongly assumed that for ROMWBW IO ports the not decoded A3 line should probably be low, however this turns out to break ROMWBW function. I temporarily disabled evaluation of the A3 line and simply wired it true. After this I found that ROMWBW initialized properly.
  • my ACIA was not working, I needed to change the IO port in the ROM.
  • I will change the mounting holes of the mainboard to include some grounding pads and vias inside them as we see on brand manufactured mainboards. This is simply a small change to make the mainboard more solidly grounded to the chassis, which is not an actual issue but simply better to do so.
  • I need to move one IC down a millimeter or two to create more spacing for the IC packages to fit more easily.
  • I need to change the clock crystal footprint because apparantly the 32768 Hz crystals do not come in HC49S packaging. Probably I will switch to a tube shaped crystal.
  • I need to change the RESET (positive logic) line because using it in this way creates problems in my power up and reset circuits. I probably need to invert /RESET another time with an inverter and route that signal to the PPI and FDC. For the time being I separated the RESET pins from the PCB with an extra socket and wired the RESET lines manually with a resistor to ground. So far I didn't find any problems with the PPIDE or FDC even without a reset occurring on them.
  • I will see about possibly adding a trimmer capacitor to the clock generator for the TMS. This may help in the future to slightly adjust the clock for better display.
  • I will be adding some pull up resistor packs to the databus and maybe also to the address bus in several areas. This will help to improve the signal stability and reduce reflections as well. I really need to get a suitable oscilloscope to evaluate all the signals for stability and see if there are any issues that can be otherwise improved. I do have a HM205-3 scope but I am currently repairing a broken off control where I need to replace a shaft on one of the potmeters. After that I can test this scope and see if it can be sufficiently accurate at this frequency to look at the bus signals and see how I can make some improvements from actually seeing the signals. Later when I get a 20Mhz Z80 I will test and look more at the signals for that frequency.
  • The SN76489 sound generators are quite noisy. I will think about some method to disable them when they are not in use, or to initialize them at boot of the PC to become more "quiet".
  • the I/O databus is currently not working with a 74HCT245 transceiver, I am using a 74LS245 for the time being, after getting my scope operational I will do further testing to find the issue with the 74HCT245.
  • the LED pins on the ethernet connector are slightly off, but still able to assemble it onto the PCB correctly. I will adjust the LED pins a little on the next PCB revision.

Basically, that was it so far up until this point. Only a few small changes were needed to get things running on the mainboard PCB. I am very happy that the big change of using the bus transceivers didn't experience too many difficult problems. It was to be assumed that because it alters the timing that some issues might occur since I was not able to test anything before yet, but I am pleased to be able to separate the bus and buffer everything successfully according to plan. Also the I/O address decoders which I totally changed to a more standardized design were all working properly.

I was able to test one of the YM2149 sound chips which operates on the MSX standard ports, which works with the TUNE.COM CP/M program. It is working fine which confirms my YM port circuits to be correct. That also means that the second YM2149 chip will work fine with software that can support it.

I am waiting for some components to arrive from China, which is of course rather delayed because most people in China were celebrating the spring festival with their family. So I will do further soldering and testing as soon as further parts arrive. I desoldered some things from a few PC mainboards so I could at least test things sooner.

So what I have confirmed to function is:

  • ROMWBW
  • PPIDE
  • RCWDC floppy controller
  • ACIA
  • YM sound on one chip, I need to see if any software is available to test both YMs for a total of 6 channels
  • DS1302 realtime clock
  • ATX power supply control
  • power-on reset circuits
  • PS/2 keyboard interface

After receiving further parts I will be testing

  • TMS video output
  • USB direct cable connection to PC for ACIA serial output

After getting the last things tested and getting all the bus signals optimized, I will move on to have the PCBs made for the RTL8019AS ethernet chip to plug into the mainboard. After that I will probably move on to the GPU design. Possibly I will design a second revision mainboard right away, just to get rid of the wired fixes and have a 100% signal optimized system which needs no modifications as a basis to continue. I may combine the RTL plug-in board and the revised mainboard in a single PCB order from JLCPCB. Further updates will follow below on this page!